Laterally diffused metal oxide semiconductor (LDMOS) devices are generally used in high voltage applications. FIG. 1 schematically illustrates a cross sectional view of a laterally diffused n-type metal oxide semiconductor (LDNMOS) transistor 100 (also referred to herein as LDNMOS 100). LDNMOS 100 is formed on a semiconductor wafer 102-1. P-type well (also referred to herein as PW) 120-1 and n-type well (also referred to herein as NW) 124-1 are formed on the wafer 102-1. A junction between PW 120-1 and NW 124-1 is labeled as 128-1 in FIG. 1.
LDNMOS 100 includes body region 104-1, source region 108-1, drain region 112-1, and poly gate 116-1. The LDNMOS 100 also includes shallow trench isolation (STI) regions 132-1, 134-1, 136-1 and 138-1. Although not illustrated in FIG. 1, the poly gate 116-1 is coupled to one or more other components of the LDNMOS 100 (e.g., to portions of the source region 108-1, PW 120-1, NW 124-1, and/or STI region 136-1) through one or more layers (e.g., a gate oxide layer).
A channel is formed in PW 120-1 between the source region 108-1 and the junction 128-1. A width of the channel is indicated as Lch-1. Also, an extension of the NW 124-1, between the STI region 136-1 and the junction 128-1, is marked as Ld-1.
Although the LDNMOS 100 exhibits high voltage tolerance, in various applications, it is desirable to further increase the voltage tolerance of the LDNMOS device 100. Such relatively high voltage tolerance may make the LDNMOS device suitable for even higher voltage applications.
The description in this section is related art, and does not necessarily include information disclosed under 37 C.F.R. 1.97 and 37 C.F.R. 1.98. Unless specifically denoted as prior art, it is not admitted that any description of related art is prior art.